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Nordic Semiconductor /nrf51 /SPIS1 /CONFIG

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Interpret as CONFIG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MsbFirst)ORDER 0 (Leading)CPHA 0 (ActiveHigh)CPOL

CPHA=Leading, CPOL=ActiveHigh, ORDER=MsbFirst

Description

Configuration register.

Fields

ORDER

Bit order.

0 (MsbFirst): Most significant bit transmitted out first.

1 (LsbFirst): Least significant bit transmitted out first.
CPHA

Serial clock (SCK) phase.

0 (Leading): Sample on leading edge of the clock. Shift serial data on trailing edge.

1 (Trailing): Sample on trailing edge of the clock. Shift serial data on leading edge.
CPOL

Serial clock (SCK) polarity.

0 (ActiveHigh): Active high.

1 (ActiveLow): Active low.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data